Tech Manager - Physical Design

• Drive RTL-to-GDSII activities including synthesis, floor planning, power planning, , placement, CTS, routing, and signoff tasks.
• Experience on multi-voltage and multi-power domain designs using UPF and low power verification (VCLP/CLP)
• Perform dynamic and leakage power analysis (using PTPX) and optimization across design hierarchies.
• Handle subsystem-level integration, including top-level timing and physical convergence.
• Run and debug signoff timing, EM/IR drop (RedHawk/Voltus), Noise, and Formal Equivalence Checks (Formality/Conformal), Power analysis (PTPX) using industry standard tools.
• Analyze results and provide feedback to RTL/DFT teams for architectural and logic-level improvements.
• Tune EDA flow knobs and refine methodology to meet aggressive PPA (Power, Performance, Area) goals.
• Collaborate with cross-functional teams including RTL, DFT, PD Methodology, and STA.
• Mentor junior engineers and contribute to flow development and automation using Python/TCL/Perl.

• Proven experience in block/SS/full-chip level RTL to GDSII implementation.
• Deep knowledge of low power design techniques, UPF 2.x, power domain crossings, level shifters, and isolation cells.
• Signoff expertise in timing convergence, power (ptpx), and EM/IR analysis (RedHawk/Voltus)
• Strong debugging and convergence skills in synthesis, placement, and routing for better QoR.
• Experience with Fusion Compiler and/or ICC2, Innovus, and PrimeTime, PTPX, Redhawk, Conformal, CLP/VCLP
• Familiarity with Python, Perl, or Tcl scripting for automation.
• Prior experience in methodology tweaking, physical-aware synthesis, and ECOs.

• Drive RTL-to-GDSII activities including synthesis, floor planning, power planning, , placement, CTS, routing, and signoff tasks.
• Experience on multi-voltage and multi-power domain designs using UPF and low power verification (VCLP/CLP)
• Perform dynamic and leakage power analysis (using PTPX) and optimization across design hierarchies.
• Handle subsystem-level integration, including top-level timing and physical convergence.
• Run and debug signoff timing, EM/IR drop (RedHawk/Voltus), Noise, and Formal Equivalence Checks (Formality/Conformal), Power analysis (PTPX) using industry standard tools.
• Analyze results and provide feedback to RTL/DFT teams for architectural and logic-level improvements.
• Tune EDA flow knobs and refine methodology to meet aggressive PPA (Power, Performance, Area) goals.
• Collaborate with cross-functional teams including RTL, DFT, PD Methodology, and STA.
• Mentor junior engineers and contribute to flow development and automation using Python/TCL/Perl.

• Proven experience in block/SS/full-chip level RTL to GDSII implementation.
• Deep knowledge of low power design techniques, UPF 2.x, power domain crossings, level shifters, and isolation cells.
• Signoff expertise in timing convergence, power (ptpx), and EM/IR analysis (RedHawk/Voltus)
• Strong debugging and convergence skills in synthesis, placement, and routing for better QoR.
• Experience with Fusion Compiler and/or ICC2, Innovus, and PrimeTime, PTPX, Redhawk, Conformal, CLP/VCLP
• Familiarity with Python, Perl, or Tcl scripting for automation.
• Prior experience in methodology tweaking, physical-aware synthesis, and ECOs.

Quest Global