
Digital Design Manager, Silicon
- Bangalore, Karnataka
- Permanent
- Full-time
- Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
- 15 years of experience in ASIC RTL design.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with ARM-based SoCs, interconnects and ASIC methodology.
- Master’s degree in Electrical Engineering or Computer Engineering.
- Experience driving multi-generational roadmap for IP development.
- Experience leading interconnect IP design team for low power SoCs.
- Lead a team of people to deliver fabric interconnect design.
- Develop and refine RTL design to aim power, performance, area, and timing goals.
- Define details such as interface protocol, block diagram, data flow, pipelines, etc.
- Oversee RTL development, debug functional/performance simulations.
- Communicate and work with multi-disciplined and multi-site teams.