Associate I - VLSI

Bangalore, Karnataka
Permanent
Full-time

1 month ago

Job Description:Role Proficiency:Works under supervision and guidance to execute internal tasks in any field of VLSI Frontend Backend or Analog designOutcomes: * Works as an individual contributor and on any one task of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.

Complete the assigned task in the defined domain(s) successfully and on-time with support from other team members and senior engineers
Ensure quality delivery as approved by the senior engineer

Measures of Outcomes: * Quality –verified using relevant metrics by Lead

Timely delivery - verified using relevant metrics by Lead
Reduction in cycle time and cost using innovative approaches
Number of trainings attended

Outputs Expected:Technical Skills: * Build up required technical skills and design knowledge to execute the assigned tasksQuality of the deliverables: * Clean delivery of the module in-terms of ease in integration at the top level

Meeting functional spec / design guidelines at least 80% of the time without deviation or limitation
Documentation of tasks and work performed

Timely delivery: * Meeting project timelines as set forth by the team lead

Help with intermediate tasks delivery with other team members to aid progress

Teamwork: * Participation in teamwork at the time of need

Able to take on additional tasks incase of any team member(s) is not available

Innovation & Creativity: * Understand how to approach repetitive work by automating taskssaving design cycle time * Participation in technical discussiontraining
forumSkill Examples: * Languages and Programming skills: System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)

EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
Technical Knowledge: (any one)a. Learn to understand IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Theoretical knowledge in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Fair knowledge of Physical Design / Circuit Design / Analog Layout d. Fair understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verification
Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
Able to deliver the tasks with quality at least 80 % on-time per quality guidelines and GANTT
Good communication skills
Good analytical reasoning and problem-solving skills and attention to details
Ability to learn new skills in case required technical skills are not present at a level needed to execute the project

Knowledge Examples:

Basic understanding in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
Understanding of the design flow and methodologies used in the designing
Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the manager per skill set

Additional Comments:Job Description: Job Requirement:. Engineers need to work closely with the IP teams and run CI-CD tasks for all the design and verification checks. Skill set requirement: Python and Shell scripting expertise in Linux environment Experience: 3-7 yearsSkills:CAD Automation Engineer ,Python,Linux EnvironmentAbout Company:UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

UST

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