Your responsibilities will include Implement technical risk assessment and NUDD (New, Unique, Different, Difficult) analysis when new designs, circuit, device, layout and process and lead execution of risk mitigation Developing and implementing test methodologies to evaluate wafer-level and circuit-level PRODUCT reliability behavior and performance. A solid understanding of semiconductor device physics and circuit operation. Basic knowledge of NAND memory and semiconductor process technology Proficiency in statistical data analysis. Exceptional communication skills are essential, along with 3 to 8 years of experience in the semiconductor industry or a research institute. Expertise in semiconductor device parametric measurement and proficiency in operating semiconductor lab instrumentation for electrical characterization are highly valued. Good understanding of Advanced CMOS Device Engineering and NAND integration. Educational qualifications include an M.S. or Ph.D. in Electrical Engineering, Physics, Materials Science, or a related field with at least 2 years of experience.
