
Principal Engineer, STA
- Bangalore, Karnataka
- Permanent
- Full-time
- As a Principal full chip STA engineer , you will be responsible for running/supporting/maintaining the Global Timing Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
- Experienced in IP constraint development and integration, constraint management and pushdown, ECO flows is a must.
- Work with design teams across various disciplines such as Digital/RTL/Analog/DFT in helping them take their blocks (custom, PnR) through the global timing flow and making sure all the blocks meet timing requirements.
- Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
- Writing scripts in TCL and Perl to achieve productivity enhancements through automation.
- BSEE or MS with 12+ years of experience running an industry standard EDA tool for global timing is required (PrimeTime preferred).
- Experience in tape-outs of high performance SOC is highly desired.
- Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation.
- Knowledge of scripting languages such as Perl/TCL is required.
- Diligent, detail-oriented, and handle assignments with minimal supervision.
- Must possess good communication skills, self-driven individual and a good team player.
- #LI-MN1