
ASIC RTL Design/Integration Lead
- Bangalore, Karnataka
- Permanent
- Full-time
- Define and specify micro-architecture of ASIC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
- RTL design and debug of complex blocks in Verilog / System Verilog
- Analyze design metrics and make implementation choices to optimize PPA
- RTL Integration
- Work with implementation, verification and physical design teams to achieve high quality design and successful tape out
- Address customer problems through innovative enhancements to product architecture/ micro-architecture
- Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms
- Lead internal and external teams for RTL design
- Strong foundation in SoC architecture and processor systems with proven years of experience
- Good analytical problem solving, and attention to details
- Excellent written and verbal communication skills
- Knowledge of CPU, AXI Interconnect, and I/O peripherals
- Knowledge of SOC development flow and accelerator IP
- Must have worked with third party contractors
- ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes
- Digital design and experience with RTL design in Verilog/System Verilog
- Circuit timing/STA, and practical experience with Prime Time or equivalent tools
- Low power digital design and analysis
- Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
- TCL, Perl, Python scripting
- Version control systems such as Perforce, ICManage or Git
- Strong verbal and written communication skills
- Ability to organize and present complex technical information
- Fluent in working with Linux environment
- BS, MS or PhD degree in in Electrical Engineering or Computer Science. 12+years of experience in an ASIC leadership role leading to an understanding of end-end development.
- Experience in leading complex subsystem or SOC level integration, quality cleanup and delivery to DV, physical design teams
- Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design techniques, security
- Strong technical leader who communicates well with great collaboration skills
- Good understanding of other domains like pre-si verification, Synthesis, physical design