Senior Verification Engineer
Arm
- Bangalore, Karnataka
- Permanent
- Full-time
- As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC.
- Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy.
- Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules.
- Should possess a good understanding of media data flow between CPU, GPU, VPU, DPU, DMA with DDR.
- Owns test development for IO Virtualization, Protection, Security, Debug and Telemetry across SoC.
- Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development.
- Senior engineers are also encouraged to support junior members.
- 5+ Yrs of Experience
- Worked on embedded C/C++ based SoC verification environments
- Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
- Experienced in one or more of various verification methodologies – UVM/OVM/eRM, formal, low power, emulation
- Exposure to all stages of verification: requirements collection, creation of verification methodology plans, testplans, testbench implementation, Testcases development, documentation and support
- Ability to work under time-scale pressure and meet aggressive targets without compromising on quality
- Understanding of the fundamentals of Arm system architectures
- Practical experience of working on Processor based system designs
- Possess knowledge of object-oriented programming concepts
- Exposure to Media IPs such as GPU, VPU & DPU and IO peripherals such as USB & UFS controllers is desirable!
- Exposure to GLS and Post Silicon Validation and their flow will be desirable.