A RTL Design Engineer with 9-15 years of experience is a senior-level position in semiconductor companies responsible for designing and implementing Register Transfer Level (RTL) logic for complex digital integrated circuits. The job description for this role typically includes the following responsibilities and qualifications: Responsibilities: RTL Design: Design and implement RTL logic for digital circuits, including microprocessors, ASICs, FPGAs, and SoCs, using hardware description languages such as Verilog and VHDL Architecture Development: Work closely with architects and system engineers to define and develop RTL architectures that meet performance, power, area, and timing requirements Microarchitecture: Develop microarchitectural specifications, block diagrams, and RTL coding guidelines for efficient and scalable designs Synthesis and Optimization: Optimize RTL code for area, timing, and power using synthesis tools and techniques, and collaborate with physical design teams for implementation and timing closure Verification Support: Work with verification engineers to develop and review testbenches, test cases, and functional simulations to verify RTL functionality and performance Design Constraints: Define design constraints, timing constraints, and clock domain crossing (CDC) requirements to ensure proper functionality and timing closure Design for Testability (DFT): Implement DFT features such as scan chains, Built-In Self-Test (BIST) structures, and boundary scan for testability and manufacturing test coverage Documentation: Create and maintain design specifications, RTL coding documents, design reviews, and design documentation to ensure clarity, traceability, and compliance with design standards Collaboration: Collaborate with cross-functional teams, including verification, synthesis, physical design, software, and system validation teams, to ensure successful tape-out and product release Qualifications: Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Experience: 9-15 years of experience in RTL design for digital integrated circuits, including experience with complex designs, high-speed interfaces, and multi-clock domain architectures RTL Languages: Proficiency in hardware description languages such as Verilog, VHDL, and SystemVerilog for RTL design and verification EDA Tools: Experience with industry-standard EDA tools for synthesis, simulation, and timing analysis, such as Synopsys Design Compiler, Cadence Encounter, Mentor ModelSim, etc Microarchitecture: Strong understanding of microarchitecture concepts, pipelining, data paths, control logic, and memory subsystems for efficient and optimized designs Design Methodologies: Familiarity with design methodologies such as ASIC design flow, FPGA design flow, low-power design techniques, and design for manufacturability (DFM) considerations Verification Skills: Knowledge of digital design verification principles, testbench development, simulation techniques, and functional coverage analysis Communication and Collaboration: Excellent communication, teamwork, and problem-solving skills to collaborate effectively with cross-functional teams, resolve design issues, and drive project success Overall, an RTL Design Engineer with 9-15 years of experience plays a critical role in developing high-performance, low-power, and reliable digital integrated circuits, contributing to the success of semiconductor products in various applications and industries Powered by JazzHR w3yNRm1xiW