
Lead RTL integration Engineer - IP/subsystems
- Bangalore, Karnataka
- Permanent
- Full-time
- Design of IP and subsystems with integration of AMD and other 3rd party IPs
- Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs
- Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
- Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up
- 8-12 years full-time experience in IP hardware design
- Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
- Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
- Clock domain crossing (CDC) tools
- Detailed understanding of SoC design flows
- Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
- Experience with embedded processors and data fabric architectures (NoC)
- Outstanding interaction skills while communicating both written and verbally
- Ability to work with multi-level functional teams across various geographies
- Outstanding problem-solving and analytical skills