DV Lead Engineer

• Develop and execute Systemverilog/UVM Testbenches for SOC/IP Verification
• Develop Test plan, Implement & run directed, random, and constrained random tests
• Write C & SV/UVM based tests
• Debug simulation failures and work with RTL team for resolution.
• Functional & code coverage analysis and sign-off checklist closure.

• Expertise in sv-uvm and C based verification environment
• Knowledge of ARM core, AXI protocol
• Experience in porting IP level SV-UVM environment to SS level
• Debugging failures at SS level
• GLS debug and bringup expertise
• Good to have Emulation debug, post silicon debug, system level test-case creation
• Language/Methodoglogy : C, SV,UVM
• Good to have python knowledge
• Excellent communication skills and willing to work on fast pace environment.

Quest Global