Senior Hardware Verification Engineer

NXP Semiconductors

Bangalore, Karnataka
Permanent
Full-time

25 days ago

Today’s SOCs have demanding security goals. These goals are critical for future security applications ranging from hardware designs to strong end-to-end solutions. The security verification team is responsible to qualify that the design architecture and implementation meets these security goals with detailed metrics analysis and cross correlation across model, RTL and emulation.In this role:

The candidate is expected to understand the IP design architecture / functionality to extract features and develop verification Test Specification
Proven experience in SV UVM test bench development to build IP level verification environment and define verification plan to achieve functional coverage targets
Define and develop robust verification plan with positive & negative test scenarios to stress the design / architecture for finding functional bugs and performance bottlenecks if any
Ability to understand the security IP specification, scope of verification to test System / SoC level use cases, subsystem / IP level requirements to achieve functional coverage targets.

Some of the challenging responsibilities include:

Designing / developing and tracking of verification plan and corresponding scenarios with understanding of Use Case and hardware systems.
Verification of hardware architectures with respect to security subsystems and cryptographic functions.
Identifying the verification strategy for security related features in subsystems and co-processors.
Be up-to-date with emerging verification techniques and introducing them into the existing verification flow.

To ensure your successful performance in this role, the following is desired:

Self-driven engineer with proven experience in digital IP & SoC verification & good communication skills
Hands on experience in CPU based Sub system/SoC level verification & debugging fails independently.
Strong skills in IP/Sub System verification & debugging in SV/UVM based environment with good problem-solving skills
Experience in developing SV/UVM test benches for IPs with very good knowledge in constraint random verification concepts
Hands-on experience on writing System Verilog assertions and understanding of Formal flow /methodologies is desirable.
Proven experience in verification sign-off at IP/Sub System/SoC level with test plan development, functional & code coverage analysis
Experience in verification of CPU based SoC & IPs like UART, Memory controllers, AHB/AXI/APB, DMA, Interrupts, Reset blocks etc..

NXP Semiconductors

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