
ASIC RTL Integration Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 8 years of experience in high-performance design, multi-power domains with clocking.
- Experience in multiple SoCs with silicon success.
- Experience with Verilog or System Verilog language.
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Experience with chip design flow and an understanding of cross-domain involving DV/DFT/Physical Design/Software.
- Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
- Lead a team of ASIC RTL engineers on sub-system and chip-level Integration activities including plan tasks, hold code and design reviews, code development of complex features.
- Interact closely with architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and performance, power, and area (PPA) for sub-system/chip-level integration.
- Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.