Power Management Design Architect (PMU/PMIC)

Best NanoTech View all jobs

  • Noida, Uttar Pradesh
  • Permanent
  • Full-time
  • 12 hours ago
  • Apply easily
1. Job TitlePower Management Design Architect (PMU/PMIC) 2. Location, Work Mode, Experience RangeLocation: Noida, India
Work Mode: Onsite
Experience: 5 15 Years 3. Role OverviewWe are looking for a Power Management Design Architect to lead the architecture, design, and validation of PMU/PMIC solutions. The role involves end-to-end ownership from concept to silicon validation. The candidate will work on DC-DC converters, LDOs, and key analog building blocks for power-efficient semiconductor systems. 4. Key Responsibilities
  • Define and develop end-to-end PMU/PMIC architecture
  • Design DC-DC converters (Buck/Boost) and LDO regulators
  • Architect and design key analog blocks such as bandgap reference, error amplifier, and gate drivers
  • Develop and optimize control loops, compensation, and stability
  • Drive power efficiency, transient response, and low quiescent current performance
  • Ensure design robustness across PVT (Process, Voltage, Temperature) variations
  • Perform simulations, design verification, and corner analysis
  • Lead silicon bring-up, debugging, and characterization activities
  • Analyze lab data and correlate with simulation results
  • Collaborate with layout, digital, and system teams for design integration
  • Mentor junior engineers and provide technical guidance
  • Support product-level validation and documentation
5. Required Qualifications
  • M.Tech or PhD in Electronics / Electrical Engineering or related field
  • 5 10 years of experience in Analog / Power IC Design
  • Proven track record of successful silicon in PMIC or DC-DC designs
  • Strong fundamentals in analog and power electronics design
6. Technical Skills (Grouped & Structured) Power Management Design
  • PMU / PMIC architecture design
  • DC-DC converters (Buck / Boost)
  • Low Dropout Regulators (LDOs)
Analog Circuit Design
  • Bandgap reference design
  • Error amplifier design
  • Gate driver circuits
  • Compensation and control loop design
Performance Optimization
  • Stability analysis and loop compensation
  • Power efficiency optimization
  • Transient response tuning
  • Low-power / low quiescent current design
Process & Validation
  • PVT analysis (Process, Voltage, Temperature)
  • Silicon bring-up and lab validation
  • Debugging and characterization
Tools & Simulation
  • Cadence Virtuoso
  • Spectre
  • MATLAB
Technology Exposure
  • CMOS / BCD process technologies
7. Good to Have (Optional)
  • Experience in automotive or low-power applications
  • Exposure to system-level power management
  • Knowledge of EMI/EMC considerations in power design
  • Experience working across multiple technology nodes
#LI-VA1

Best NanoTech