Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

In-depth understanding of high-speed Serdes/Memory interface circuits like I/O’s,PLL’s, Clocking, Datapath’s.
Hands on experience on PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits.
Strong Analog Design and I/O Design fundamentals. Knowledge of ESD/Reliability/SI/PI.
Experience in leading complex IP’s , managing cross functional dependencies needed.
Experience in leading and mentoring Junior Engineers.
Must have excellent written and verbal communication skills as well as good problem-solving skills.
Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage.

We’re doing work that matters. Help us solve what others can’t.