Design Engineer II
- Pune, Maharashtra
- Permanent
- Full-time
- BTech/ MTech in Engineering with 3 to 6 years of actual work experience in RTL Design.
- The ideal candidate should have thorough understanding of end-to-end Digital design flow.
- Verilog / System-Verilog RTL logic design, debug, and functional verification support.
- Understanding of proper handling of multiple asynchronous clock domains and their crossings
- Understanding of Lint checks and proper resolution of errors
- Working experience on APB and AXI protocols.
- Working experience on micro-controller based designs and its associated logic is a Strong plus.
- Experience in Digital microarchitecture definition and documentation is a plus
- Experience in synthesis timing constraints, static timing analysis and constraint development is a plus
- Experience with FPGA and/or emulation platform is a plus.
- Exhibit excellent communication skills and be self-motivated and well organized.