DV Lead Engineer

• Lead end-to-end DV activities : Testbench architecture, Test plan, Coding, execution and Sign-off.
• Strong knowledge in CPU based SOC architecture.
• Develop and execute System Verilog/UVM Testbenches for SOC/IP Verification
• Develop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random tests
• Analyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution.
• Define Functional/Code/Assertion coverage metrics and sign-off checklist and drive to closure.
• Mentor & Drive Junior Team, conduct reviews and ensure quality.

• Expertise in sv-uvm and C based verification environment for SOC
• Knowledge of ARM core, AXI protocol, tarmac debug, basic assembly code.
• Debugging failures at SOC level
• GLS debug and bringup expertise
• Good to have Emulation debug, post silicon debug, system level test-case creation
• Language/Methodoglogy : C, SV,UVM
• Good to have python knowledge
• Excellent communication skills and willing to work on fast pace environment.

Quest Global