AMS Verification - Lead Engineer
- Hyderabad, Telangana
- Permanent
- Full-time
- BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification
- Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks
- Very Good experience in Analog Mixed Signal verification simulation tools
- Good experience in System Verilog, UVM methodologies
- Able to train the team members and guide them to the solutions for problems
- Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch.
- Good experience in Gate level netlist simulation
- Experience in Python, Perl, Shell scripting is added advantage.
- Good communication and documentation skills