Senior Staff Engineer - IO Circuit Design
Marvell
- Bangalore, Karnataka
- Permanent
- Full-time
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.What You Can ExpectYour role involves conducting in-depth circuit analysis for compact sub-circuit blocks within our overall design, considering Process, Voltage, and Temperature (PVT) factors.Using your experience using transistor-level circuit design software like Cadence Virtuoso or Spectre X for design analysis, you will be mentoring others to optimize performance within specified area and power constraints, utilizing engineering judgment to balance trade-offs and refine designs.Tools such as Python, Perl, and the Microsoft Office Suite will be integral to your tasks, and proficiency in a Linux environment is essential for seamless execution.Design and deliver I/O libraries supporting various industry standards and custom analog circuits to customer specifications including the generation and delivery of final EDA views for the IPs. The I/O libraries include GPIO, over voltage protected I/O pads, LVDS, SSTL, HSTL, ISLVS, I2C, I3C, 3D IO and support cells.Design and deliver the custom analog circuits to customer specifications including the generation and delivery of final EDA views for the IP. The Analog circuits include amplifiers, Bandgap, ADC/DAC, and LDOs power switches, biasing blocks, over-voltage/over-current protection circuits, power-switches and a range of closed loop feedback circuits.Provide the required technical guidance and support to SOCs, and test chips for I/O hardware qualification, failure analysis, issue root cause determination, and the development of corrective actions.Continue the development and improvise “best practices” and “design checklist” for circuit design.What We're Looking ForTo be successful in this role, you must:Bachelor’s or Master’s degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields and 7-12 years of relevant professional experience.Advanced knowledge and hands one experience with I/O design to support various I/O standards, on-chip ESD protection circuit design using CAD design tools such as Cadence virtuoso and Synopsys DC.Applicant should have sufficient design experience to be able to effectively own and review circuit and layout designs.A very good knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operationsComprehensive simulation skills in Cadence including PEX, Monte Carlo, and Corner analysis.Derive design specifications from customer requirement.Hands-on experience with standard analog cell design including bandgaps, op-amps, detectors, regulators, precision current source and amplifiers.Identifies and proposes innovative solutions to enhance the design of at least one major sub-circuit block.Participates in root cause investigation and silicon validation of model to hardware correlation issues.Mentors and coaches new and/or less experienced team members.#LI-CP1Additional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our page.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.