Job RequirementsJob Summary:We are seeking an experienced RTL Technical Lead Engineer to take ownership of RTL design and provide technical direction for complex digital blocks or SoCs. The ideal candidate will combine deep design expertise with leadership and cross-functional collaboration skills.Key Responsibilities:Lead RTL design and micro-architecture development for IP/SoC components. Translate design specifications into efficient and high-quality RTL code (Verilog/SystemVerilog).Drive technical reviews, architecture discussions, and RTL delivery schedules. Interface with verification, synthesis, DFT, and physical design teams. Ensure design quality through lint, CDC, and synthesis checks. Guide and mentor junior engineers and review their work. Debug design issues and support integration and bring-up.Preferred:Experience in low-power design, multi-clock domains, and power intent (UPF).Familiarity with industry standards like PCIe, USB, DDR, Ethernet, etc.Prior experience as a technical lead or team coordinator.Work ExperienceRequired Skills and Experience:9+ years of hands-on RTL design experience in the semiconductor/VLSI industry. Strong expertise in Verilog/System Verilog and digital design fundamentals. Good understanding of SoC integration, bus protocols (AXI, AHB), and timing constraints. Experience with tools like Synopsys/VCS, Spy Glass, Design Compiler, and Prime Time. Strong analytical and problem-solving skills.
