
Lead Silicon Design Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
- Own verification strategy and execution for complex Data Fabric IP blocks and subsystems from spec review through tape-out.
- Define and architect UVM-based testbench infrastructure for scalability, reusability, and high coverage across product generations.
- Lead test plan creation and sign-off, integrating both constrained-random and directed testing methodologies.
- Drive coverage-driven verification — define, track, and close both functional and code coverage goals.
- Collaborate cross-functionally with design, architecture, and performance teams to debug complex issues and ensure first-pass silicon success.
- Mentor and guide junior and mid-level verification engineers, reviewing their code, test plans, and coverage results
- Identify and drive verification methodology improvements, automation, and process optimizations to enhance team productivity.
- Participate in post-silicon debug and validation, assisting in recreating and root-causing issues found in lab or customer systems
- Expertise in SystemVerilog & UVM for block- and system-level verification of complex IP.
- Proven track record of leading verification on large, high-performance ASICs or SoCs from concept to tape-out.
- Strong knowledge of computer architecture and interconnect/fabric protocols.
- Proficiency in EDA tools such as Synopsys VCS
- Advanced debug skills for simulation and waveform analysis.
- Scripting proficiency in Python, Perl, or similar for automation and flow development.
- Experience with coverage closure strategies, regression management, and verification metrics reporting.
- Familiarity with formal verification concepts and tools is a plus.
- Bachelors or Masters degree in computer engineering/Electrical Engineering
- #LI-BM2