
Senior Technologist, ASIC Development Engineering (IO Design)
- Bangalore, Karnataka
- Permanent
- Full-time
- Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering
- Working experience (20+ years) in IO including 5+ years as a project leader
- Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization
- Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/LPDDR4/LPDDR5 along with timing budget analysis.
- Should be experienced in high speed design architectures such as SERDES, Equalization schemes
- Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc.
- Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff
- Experience in full custom high speed data path design such as DDR PHY will be of advantage.
- Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies
- Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage.
- Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage.
- Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm/7nm/5nm and the associated DFM issues.
- Very analytical in nature and able to work in a multi-disciplinary environment
- Creative, out-of-the-box thinker with a high level of personal involvement
- Strong theoretical background with a pragmatic approach.
- Good verbal and written communication skills and experience working with different geographies.
- Good mentoring, documentation and presentation skills