Senior Staff Engineer Design

Bangalore, Karnataka
Permanent
Full-time

6 hours ago

Experienced in generating top-level functional vectors for IPs used in production and characterization testing. Skilled in SystemVerilog and SoC-level verification with a strong ability to debug tester failures. Possesses solid analytical and debugging skills, along with foundational knowledge in Verilog/VHDL design techniques and simulation flows. Familiar with UVM methodology and basic Perl scripting.Job Description

Responsible for generating top-level functional vectors for IP's for production and Char testing.
Knowledge of System Verilog.
Experience with SOC level verification.
Experience in Tester failure debugs.
Excellent analytical and debugging skills.
Basic knowledge in design techniques Verilog or VHDL.
A good knowledge of simulation flow.
UVM knowledge a plus.
Perl basics a plus.

Your Profile
You are best equipped for this task if you have:

ASIC flow understanding.
The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, and Post silicon debug.
In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies.
The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Scripting skills such as PERL/TCL/Python are preferred.

Degree & Discipline:

BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design.

Experience in Industry:

10+ years of in DFT implementation, verification and post silicon debug areas.

Contact:
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