
Sr Principal Engineer - RTL Design
- Noida, Uttar Pradesh
- Permanent
- Full-time
- Design and implementation of Interconnect for next gen SoC design.
- Work with System architects and IP design owners to understand requirements for optimal implementation of interconnect.
- Prior experience with Arteris Flexnoc/NIC/NoC will be an added advantage.
- RTL development including tool flows like lint, CDC and synthesis.
- Knowledge of standard bus protocols mandatory for efficient interconnect design.
- Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams.
- Provide support to SoC integration and chip level pre/post-silicon debug.
- Work closely with Functional verification, performance verification and emulation teams to ensure all requirements are verified in pre Silicon environments.
- Provide post Silicon support related to device performance to validation and SW teams.
- MTech/BTech in EE/CS with hardware engineering experience of 12+ years.
- Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.
- Ability to understand IP needs and translate to optimal Interconnect design needs.
- Experience with post-silicon bring-up and debug is a plus.
- Able to work with teams across the globe and possess good communication skills
- Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
- Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people's lives easier, safe and secure.
- Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.