
IP/RTL Design Lead
- Bangalore, Karnataka
- Permanent
- Full-time
- 6 to 10 years of working experience in ASIC design
- Proficiency in Verilog/SystemVerilog RTL
- Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification.
- Active knowledge of ASIC design quality flows
- Knowledge of cache coherency and /or fabric /NOC design is a plus
- Low power analysis and design
- Version control systems such as Perforce, Git
- Bachelors or Masters degree in computer engineering/Electrical Engineering