Senior Principal Engineer

• Embedded FW that runs on our RISC-V-based multi-core MCU, which controls our proprietary DSP data path
• C SDK provided to customers for interfacing and controlling our product
• Python-based GUI for in-field debug, status, and control
• Build, test, and automated regression infrastructure for the above

• The technical or project lead on a product, driving the whole SW team dedicated to that project (2-8 other developers) through the development process from collecting requirements to volume production
• Responsible for the overall Architecture, Design, Development, and Testing of embedded C firmware for controlling our extremely complicated DSP HW
• Taking lead on difficult to debug issues, drive to root causes with HW/Systems teams, and follow up with test/validation/customer support teams to make sure the issue is resolved
• Working with the cross-functional team to plan SW milestones, develop in sprints, closing tickets, work with multiple test disciplines, squash all the bugs, and roll out features for the product as a whole
• Distilling complex systems specifications from standards bodies (MSA/OIF/CMIS) or directly from the customer into easy-to-digest internal documentation, definition of requirements, and clear sequence diagrams to aid in development.
• Traveling to offices worldwide for product development and chip bring-up (~3weeks/yr, California, Italy, Vietnam)

• Mentoring a Jr engineer while working on a difficult HW/SW debug together
• Developing the use cases, architecture, and system diagrams for a complicated new feature, and integrating that feature into the existing FW & Customer SDK to be as seamless as possible
• Convert computationally heavy floating point matlab algorithms into fixed point firmware state machines, and coming up with simple ways to compare the two to guarantee functional correctness
• Working with leads in other teams to develop a post-silicon system test plan for a brand new product
• Using production FW against the DV simulation environment to root cause a complicated sequencing issue only seen in the field
• Convincing a large group hardware designers to make changes in next generation products to improve field usability

• Minimum Requirements:

• Bachelors/Masters degree in CSE/ECE or related technical field(s)
• 15+ years of experience in memory constrained embedded C/C++ FW development
• SW Team Lead or Technical Lead on embedded projects; project management & release planning, architecture design & development, code reviews & testing, through to customer volume production
• Understanding of embedded SoC, micro-controller architecture (RISC-V architecture a plus), memory-mapped hardware interfaces, GPIOs, ISRs, etc.
• Excellent verbal and written communication skills in English, and able to collaborate in a large cross functional organization
• Excellent problem-solving and customer debug skills on real hardware in the lab
• Experience with using revision control and defect tracking systems (git & Jira or similar)

• Preferred but not required:

• Experience with SERDES, IM-DD/Coherent DSP, Ethernet/PCIe PHYs, and/or Optical Module SW
• Experience with designing/developing/debugging software state machines, transitions, context saving, error handling
• Experience with mixed-signal (analog+digital) control and monitoring, PID/feedback loop control, etc.
• Experience with bare-metal, RTOS, device driver, Linux kernel, etc.
• Familiarity with advanced compiler options and details (clang/gcc preferred)
• Proficient in C and Python, with knowledge of git, Linux, makefiles, gdb, IDEs, bash, etc.
• Familiarity with digital verification test flows, FPGA emulation, hardware languages such as Verilog
• Familiarity with lab equipment such as oscilloscopes, supplies, PNAs, ONTs, etc.
• Understanding of networking from the OSI model, with emphasis on the PHY up to the data link level
• Understanding of signal processing: histograms, BER, SNR, sampling phase, Shannon limit, impulse & frequency response, FFT, etc.

Marvell