Lead Design Engineer

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a We have an immediate opening in the System Validation team at Cadence Design Systems Bangalore, for the post of "Lead Design Engineer (IP System Validation)" (Grade “T3”).
• Job Title: Lead Design Engineer
• Location: Bangalore
• Job Summary
• The responsibility primarily entails pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.
• What we do :
• • Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators.
• • Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team)
• • Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet.
• • Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release.
• • Engage in interop and Customer Debug.
• Job Responsibilities
• What you'll gain :
• • Chance to work on cutting edge SERDES IP's from Cadence. Refer to Cadence Website for more details on our SERDES IP's.
• • Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration.
• • Hardware and Subsystem design expertise.
• • Experience in deploying and debugging your Solutions in different customer environments.
• Minimum Qualifications:
• BE/BTech/ME/MS/MTech in Electrical/Electronics

• • 5-7 years (with Btech) or 5 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• • Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
• • Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
• Preferred Qualifications:
• • Experience in PCIe/UCIe LTSSM states is a plus.
• • 1-2 years of experience in FPGA Design and Schematic design is a plus.
• • 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
• • Familiarity with Verilog RTL coding for FPGA, python,C/C++
• • Good communication skills
• • Candidates are expected to be passionate about analog and digital electronic circuit design.iverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

Cadence Design Systems