SOC Physical Verification Lead
GlobalFoundries
- Bangalore, Karnataka
- Permanent
- Full-time
- Well versed in DRC,LVS and ERC checks and fixes . Prior work experience in the ASIC and Top level verification domain is a must.
- Well conversant with different verification methodologies like assertion, function and test coverage with good understanding of test generation process.
- Experience in Virtuoso Layout editor is a must .
- Knowledge on low power design and verification methods
- Expertise in quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc.,
- An expert user of one or more of the following verification tools: across Cadence, Synopsys and Mentor Graphics
- Developing design, verification and validation tools and flows, Work with the verification engineers to help on the verification strategies and participate in test plan and coverage reviews
- Analytical problem solving and troubleshooting skills (e.g. debugging, Functional simulation debugging, Script debugging )
- Mentor less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones
- Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.
- Requires Master’s Degree (MS/MTech) or Bachelor’s Degree with Specialization in Computer Engineering or Electrical (VLSI, Microelectronics and related fields) from a reputed university.
- B.S. + minimum of 8-10 years of relevant experience
- M.S. + minimum of 7 years of relevant experience
- PhD + minimum of 5 years of relevant experience
- Minimum of 10 - 12 years of experience with SOC Design (RTL to GDS) and simulation
- Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys…) tools for Front End and Back End design & simulations (DC/Genus, ICC2/Innovus , Virtuoso, Spectre, HSPICE, etc.)
- Experience in RTL Coding and Verification, Place and Route and SignOff EMIR, STA and PV
- Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs
- Must have good technical verbal and written communication skills and ability to work with cross functional teams
- Be able to collaborate with program and technical design leads on multiple concurrent projects.
- Knowledge in various technologies (Bulk, CMOS & SOI) process is desired
- Experience in Silicon debug and design validation is a plus
- Patents and publications will be a good advantage
- Exceptional Spoken and Written Proficiency in English
- Strong analytical and problem-solving skills.
- Strong ability to learn and explore new technologies, opportunities, and continuous improvement.
- Ability to interact effectively with both external and internal customers at all levels and from various cultural backgrounds.