Senior Staff to Principal Engineer - ESD Design
- Bangalore, Karnataka
- Permanent
- Full-time
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.What You Can Expect
- Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness.
- Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to 2nm across major foundry platforms.
- Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation, and any other industry methods and tools.
- Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools.
- Continue the development of “best practices” for ESD in the technologies being supported.
- Development and support of EDA tools for ESD design checking.
- Development of circuits like Driver, Receiver, Overvoltage protection circuits, Fail safe I/O, Bandgap and Voltage Regulators.
- Bachelor’s or Master’s degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields and 8-15 years of related professional experience.
- Expertise in custom circuit design, handling layout effect in advanced FinFET process design rules, process variability and circuit reliability issues that affect power, speed, area, and yield.
- Advanced knowledge of on-chip ESD protection circuit design
- Advanced knowledge of CAD design tools such as Cadence and SPICE
- Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering.
- Advanced knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operations
- Fully familiar with industry ESD test standards and latest developments.
- Experience with verifying ESD analysis for IP and SoC level using industry standard tools and methodologies.
- Exposure and experience with the Custom ESD PERC code development will have added advantage to this role.
- Experience with simulation skills using cadence including PEX, Monte Carlo, and Corner analysis.
- Derive design specifications from customer requirement.
- Requires effective communication between multiple sites and ability to work with multiple groups.