Lead DV Engineer

• Develop and execute Systemverilog/UVM Testbenches for IP Verification
• Develop Test plan, Implement & run directed, random, and constrained random tests
• Debug simulation failures and work with RTL team for resolution.
• Functional & code coverage analysis and sign-off checklist closure

• 7 to 9 years of IP Verification experience with hands-on knowledge in SV/UVM
• Experience in one of the High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)
• Experience in Serdes IP Verification preferrable
• Familiarity with standard verification tools ( VCS, Xcelium) and debug environment
• Scripting skills ( Python/Perl)
• Strong debugging, analytical and problem-solving skills

Quest Global