Chip Top lead

• Lead and own the full-chip physical design flow from RTL to GDSII.
• Drive floor planning, power planning, clock tree synthesis (CTS), placement, routing, and signoff (timing, IR-drop, EM, DRC/LVS).
• Coordinate with block-level PD owners and ensure seamless integration at the chip level.
• Analyse and optimize PPA to meet design targets.
• Collaborate with RTL, STA, power, DFT, verification, and package teams for design convergence.
• Lead ECO cycles for timing, congestion, and physical sign-off closure.
• Review and debug physical verification and timing issues.
• Manage schedules, resources, and risk tracking for PD deliverables.
• Prepare and present project status, risks, and mitigation plans to management and customers.
• Mentor and guide junior engineers in the team.

• 10+ years of experience in ASIC/SoC physical design with at least 3+ years in a lead role.
• Strong expertise in industry-standard PD tools (Cadence Innovus, Synopsys ICC2, etc.).
• Proven experience in full-chip integration and signoff flows.
• Good understanding of STA (PrimeTime), physical verification (Calibre), and low-power design methodologies (UPF/CPF).
• Hands-on experience with process nodes (22nm / 28nm preferred).
• Strong debugging and problem-solving skills in timing, congestion, and physical verification.
• Familiarity with package/chip co-design and IO planning.
• Hands on experience in handling Analog custom routes, understanding the spec to meet R and C
• Good hands on experience in Full chip CTS implementation
• Good hands on experience in IO Ring creation, Partitioning, Timing budgeting, VA creation ( Design Planing activities )
• Experience in multi-voltage, multi-frequency design
• Knowledge of EM/IR-drop analysis and mitigation techniques.
• Excellent communication and leadership skills.

Quest Global