SERDES PHY Analog Design Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.Job FunctionBDC SerDes Mixed-Signal design team is actively looking for experienced (16+ years) analog circuit designers to work on high speed SerDes PHYs. You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products.Responsibilities
- Hands-on experience - Analog circuit design
- Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc.
- Analog and or Digital PLLs for frequency synthesis and/or SerDes applications
- Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers.
- PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ)
- Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.
- Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.
- For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc.
- Understanding of advance Finfet process effects on designs and layout is required.
- Experience in using SPICE simulators, adexl & virtuoso.
- Experience with post-Si bring-up and debug is must.
- Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage.
- Master/Bachelor in Electronics
- Shell/Perl-python scripting to automate circuit design and verification work.
- Able to work with teams across the globe and possess good communication and presentation skills.