Principal Engineer, Design Verification (PCIE, SV, UVM)

Marvell

Bangalore, Karnataka
Permanent
Full-time

1 month ago

About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M® product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform.As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc.What You Can Expect

Lead the DV block & take responsibility of the verification of blocks, sub-systems and top-level environment.
Develop and maintain verification environment in UVM (Universal Verification Methodology)
Define and review verification test plan with architecture team and design team
Verify the design with directed and constraint random functional parameters
Maintain regression and debug test failures with designers
Report and analyze verification coverage of design features and parameters
Drive the verification to reach coverage target

#LI-RS1What We're Looking For.

Solid knowledge and expertise in defining and developing verification testbench architecture and components.
Ability to understand design architecture and design implementation specifications to create verification test plans.
Strong PCIe Protocol Expertise
Good knowledge of SoC architecture and experience with interconnects, PCIe, and peripheral interfaces
Expertise in UVM methodology
Programming skills in System Verilog, C, C++
Scripting skills in Perl, Python or Tcl
Strong debugging skills
Strong mentoring skills
Experience with formal verification tools
Experience in FPGA prototyping and Emulation
Strong cross-functional experience and communication skills

#LI-RS1Additional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our page.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Marvell

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