ANNEXUREAbout BlaizeBlaize has developed a suite of purpose-built, full-stack programmable processor architecture and a low-code/no-code software platform that enables AI processing solutions for high-performance computing in multiple large and rapidly growing markets. Our proprietary solutions enable enterprises to harness the power of AI at the periphery of the network and in the data center and deliver real-time insights and decision-making capabilities with speed and efficiency. Our comprehensive partner ecosystem delivers turn-key solutions based on and complementing our technologies, such as cloud service providers, independent software vendors, aggregators, industrial personal computer vendors, and others. Blaize has raised $224 million from strategic investors such as DENSO, Mercedes Benz, Magna, and Samsung, financial investors such as Franklin Templeton, Temasek, GGV, and Bess Ventures, and globally-renowned operators such as Dado Banatao, Jürgen Hambrecht, Dr. Paul Achleitner, Dr. Gerhard Roiss, and Dr. Kurt Lauk. Headquartered in El Dorado Hills (CA), Blaize has more than 200 employees worldwide with teams in San Jose (CA), Cary (NC), and subsidiaries in Hyderabad (India), Leeds, and Kings Langley (UK), and Abu Dhabi (UAE).JOB DESCRIPTIONWe work on complex high performance, fully programmable, low power design of Graph Streaming Processor, an architecture specially designed for machine learning/visual applications. As a member of our focused group of HW engineering, the candidate will be involved in designing a stream processor and memory subsystem working on every aspect of hardware design and will be involved in close interactions with both SDK and backend teams for performance tuning, area, and power optimizations of multi million gate design.EDUCATION AND EXPERIENCEBE/BTech/ME/MTech in Computer Science or Electronics or Electrical8+ years of experienceREQUIRED KNOWLEDGE, SKILLS, AND ABILITIESCapability to understand a given block specification and come up with Micro ArchitectureCapability to derive an architecture and micro architecture based on a given algorithmExperience in processor design - RISC/DSP/VLIW/SIMD architectures and/or memory subsystem design, cache hierarchy design.Knowledge in digital logic for HW safety/protection - ECC, Parity, WDT etc.Experience of multi-million gate ASIC design and verification methodologiesKnowledge of Computer architectureExperience in AMBA AXI, AHB, and APB protocolsExpertise in System on Chips.Knowledge of digital design methodologies and tool flowExcellent logic design, debugging and problem-solving skills.Experience in logic design with Verilog and/or System Verilog and validation/verificationExperience in lint checks, area optimization, power optimization, GLS, synthesis and timing analysisExperience in Multi-clock domain, InterconnectsKnowledge on Memory subsystemADDITIONAL SKILLS:Knowledge in Automotive ISO 26262 Functional Safety Standard is a plus.Experience with DSP, Datapath design and floating-point math a plusKnowledge of SIMD, MIMD, VLIW, and parallel processing a plusUnderstanding of GPU/AI/ML Processor architectureLOCATIONHyderabadBlaize is an equal opportunity employer. We pride ourselves on having a diverse workforce and we do not discriminate against any employee or applicant because of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, or any other basis protected by law. We respect the gender, gender identity, and gender expression of our applicants and employees, and we honor requests for preferred pronouns. It is our policy to comply with all applicable national, state, and local laws pertaining to nondiscrimination and equal opportunity.
