Senior DFT Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
Key job responsibilities
Lead development & implementation of DFT architecture including system level DFT for a full chip
Write and guide others in writing design flow and project documentation.
Own DFT planning, milestone tracking, and cross-functional checklist reviews.
Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists.
Review and sign-off SoC level DFT mode timing closure using static timing analysis
Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon
Keep informed on and introduce new technology into Design-for-Test process as appropriate.BASIC QUALIFICATIONSEducation:
BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field.Experience:
15+ years in SoC/ASIC DFT, including 3+ years Leading DFT.
Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production.DFT Architecture Expertise:
Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including:
Scan architecture, compression, and ATPG implementation for high fault coverage and test quality.
MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration.
IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures.
DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths.
RTL and gate-level debug, including mismatch triage and simulation correlation.
Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation.Tool Proficiency:
Deep hands-on experience with Tessent / Industry Std EDA tools, including:
IJTAG ICL extraction and PDL modeling.
DFT logic insertion, pattern generation, and diagnostics.Design Background:
Experience in writing verilog/system verilog RTL related to DFT logic design.ATE Test Readiness:
Lead DFT-to-ATE handoff, including:
Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets.
Pattern validation, format conversion, and debugging across wafer sort and final test.
Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements.Silicon Debug:
Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis.Automation Skills:
Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl.Collaboration:
Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing.Execution Excellence:
Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success.PREFERRED QUALIFICATIONSLeadership:
Led multi-site/global DFT teams, mentoring engineers and managing design reviews.
Drove design-for-test planning in collaboration with customers or design services partners.Technical Depth:
Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies.
Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues.
Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement.Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.