Job RequirementsDefine and implement DFT architecture and strategy for complex SoCs and ASICsInsert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structuresDevelop and maintain ATPG (Automatic Test Pattern Generation) patterns and flowsWork closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are metDebug DFT-related issues during simulation, emulation, and silicon bring-upPerform timing analysis and constraints development for DFT logicDrive silicon validation and yield improvement initiatives related to DFTDocument DFT design and verification methodologyBachelor’s or Master’s degree in Electronics4–8 years of hands-on experience in VLSI DFTStrong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementationProficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)Good understanding of RTL design, synthesis, and timing closureExperience with silicon bring-up and production test supportExcellent problem-solving and debugging skillsStrong communication and teamwork abilitiesExperience in low-power DFT techniquesFamiliarity with scripting (Perl, Python, Tcl) for automationWork ExperienceStrong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementationProficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)Experience in low-power DFT techniquesFamiliarity with scripting (Perl, Python, Tcl) for automationGood understanding of RTL design, synthesis, and timing closure
