Synthesis (Design Implementation) Engineer - Sr Lead
Qualcomm
Bangalore, Karnataka
Permanent
Full-time
29 days ago
4-8 years of experience in ASIC synthesis Expertise in Synopsys/Cadence Synthesis tools : DC /FC/ Genus Expertise with STA with Prime Time : Good Experience in synthesis timing closure and interactions with DFT and PD. Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format) Experience in formal verification with Cadence LEC Expertise in ECO flows Experience in Spyglass Lint/CDC checks Experience in RTL HDL languages Verilog/VHDL Understanding of RTL to GDS flow Expertise in Perl, TCL language General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leads Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC Design and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed. Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
