
Verification Engineer
- Hyderabad, Telangana
- Permanent
- Full-time
- * Develop, implement, and maintain verification environments using Verilog/SystemVerilog. * Apply UVM methodology to build and enhance testbenches, ensuring thorough coverage of verification scenarios. * Perform debugging and root-cause analysis of test failures to ensure design quality. * Verify and validate AMBA protocols (AXI, AHB, APB) where applicable. * Collaborate on ARM-based SoC verification tasks (preferred, but not mandatory). * Leverage strong knowledge of digital design fundamentals to identify design and verification gaps. * Create and maintain automation scripts (Perl, Tcl, Make, Shell scripting) to improve verification efficiency. * Work closely with design, validation, and architecture teams to ensure timely closure of verification tasks.
- * 8+yrs exp * Strong verification skills with hands-on experience in Verilog and SystemVerilog. * Proven expertise in UVM methodology, with solid experience in developing testbenches. * Good debugging and problem-solving skills. * Familiarity with AMBA protocols (AXI, AHB, APB) - good to have. * Strong foundation in digital design fundamentals. * Proficiency in scripting languages (Perl, Tcl, Make, Shell scripting) for automation.
- Exposure to ARM-based SoCs preferred but not mandatory.