Intern - VLSI DI
Seagate
- Pune, Maharashtra
- Training
- Full-time
- Be able to work on block level Physical Design implementation using EDA tools for floorplanning, placement and timing analysis
- Understand Semicustom IC design flow using IP libraries, concepts of Verilog netlist, meaning of timing constraints and QOR checks
- Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing, timing analysis and equivalence checking for designs
- Work on Timing analysis for sign-off corners and modes, report generation, analysis of the reports and suggesting timing/DRC fixes to fix the violations
- Complete internship project as per plan
- Knowledge of ASIC design flow and tools
- Good understanding of Circuit design and Logic design
- Good understanding of analog circuit design and concepts
- Good understanding of timing concepts like setup time, hold time requirements, calculations of maximum
- Understanding Frequency of circuit operations, effect of transition and load on circuit performance and power
- Basic understanding of CMOS fabrication process
- Basic understanding of layout design for CMOS and BJT
- Basic understanding of power dissipation in different types of circuits
- Self-motivated & a strong team player
- Strong analytical skills
- Ability to quickly learn new tools and technologies
- ASIC design flow, basic EDA tools for Physical design implementation
- Place and Route, Timing Analysis, Equivalence check
- Perl, Tcl, Shell or other scripting languages
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