Minimum qualifications: Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience. Experience in high performance synthesis, PnR (Place and route), and sign-off optimizations. Experience in sign-off convergence, including Static timing analysis (STA), electrical checks, and physical verification. Preferred qualifications: Knowledge of Verilog/SystemVerilog. Understanding of circuit design, device physics, and deep submicron technology. Excellent scripting skills with Python, Tcl, or Perl. About the job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Develop all aspects of ASIC Register Transfer Level (RTL) description intoGraphic Data System(GDS)implementation for high power, performance, and areadesigns. Manage block and full-chip level physical implementation, power, timing, and area. Work with cross-functional teams, such as RTL and DFT, and provide feedback on quality of result issues. Manage block and full-chip level physical implementation and quality of result issues(e.g., power, timing, area).
