Collaborate with cross-functional teams to integrate DFM best practices into the design process. Develop and enhance DFM capabilities, tools, and methodologies to improve mask design quality and efficiency. Engage with the NAND Design team to provide feedback on lessons learned and best-known methods (BKMs) from DFM and high-volume manufacturing experience. Ensure Si learning is incorporated into continuous improvement efforts for design methods and tools. Work closely with the Technology Development (TD) team to support test chips and early-stage development, including collaboration with CMOS and ESD teams. Own test chip activities, including meeting organization, reticle coordination, and layout design coordination. Build Relationships across the organization through participation in innovation forums and activities, identifying technical opportunities for improvement. Collaborate with Quality teams to engage in reliability of Reliability Sensitive Circuitry (RSC) and Design Failure Modes and Effect Analysis (DFMEA) related activities. Act as a Quality representative, driving corrective 8D, and preventive actions to enhance mask design robustness and reliability. You believe in driving continuous improvement. You are an Engineer who is passionate about learning new things as well as creating and innovating. You are tenacious and motivated by new challenges. Bachelor's or master's degree in Electronics Engineering, Microelectronics, Semiconductor Physics, or a related field. 6 - 8 + Years of experience in mask design, DFM methodologies, semiconductor design and manufacturing. Strong understanding of semiconductor fabrication processes and lithography techniques. Familiarity with EDA tools for mask design (Cadence) and Verification (Calibre - DRC, LVS, Net Extraction ). Excellent problem-solving skills and ability to work in a fast-paced, collaborative environment. Effective communication skills to engage with cross-functional teams and drive improvement.
