Principal Verification Engineer
Marvell
- Bangalore, Karnataka
- Permanent
- Full-time
- Develop and maintain verification environment in UVM (Universal Verification Methodology)
- Define and review verification test plan with architecture team and design team
- Verify the design with directed and constraint random functional parameters
- Maintain regression and debug test failures with designers
- Report and analyze verification coverage of design features and parameters
- Drive the verification to reach coverage target
- Take responsibility in the verification of blocks, sub-systems and top-level environment.
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 8-15 years of related professional experience.
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
- Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
- Good scripting skills in languages such as Perl, Tcl, or Python.
- Experience in PCIe and NVMe is a plus
- Knowledge of AXI and AHB is a plus
- Good verbal and written communication skills in English