Senior FPGA RTL Design Engineer

• Location: Bangalore / Coimbatore
• Work Mode: Onsite
• Experience: 5 7 Years

• Own FPGA design projects from concept to delivery, including planning, risk management, and design reviews
• Define micro-architecture for IP/subsystems and integrate third-party IP blocks
• Partition algorithms between FPGA and software implementations
• Estimate FPGA resource utilization, memory, and bandwidth requirements
• Perform RTL design, synthesis, implementation, and timing closure on Xilinx FPGAs
• Develop module-level designs including coding, simulation, and verification
• Conduct peer reviews and ensure design quality and compliance
• Work on high-speed interfaces such as AXI, PCIe, Ethernet, JESD204B/C, DDR4, SPI, I2C, UART
• Handle multi-clock domain designs and asynchronous communication challenges
• Support system integration, validation, and production deployments
• Perform on-board debugging using hardware tools and protocol analyzers
• Collaborate with cross-functional teams during development and deployment phases

• Bachelor s or Master s degree in Electronics, Electrical Engineering, Computer Engineering, or related field
• 5 7 years of hands-on experience in FPGA RTL design and development
• Strong understanding of digital design and FPGA architecture

• RTL Design using Verilog / VHDL
• Micro-architecture definition and logic design
• FPGA synthesis, implementation, and timing closure

• Xilinx FPGA design and prototyping
• Constraints development, linting, CDC analysis
• Simulation and verification methodologies

• AMBA protocols: AXI, AHB, APB
• High-speed interfaces: PCIe, Ethernet, JESD204B/C
• Peripheral interfaces: SPI, I2C, UART, DDR4

• C / C++
• Python / Perl

• FPGA-SoC interfacing
• Hardware debugging tools: Oscilloscope, Logic Analyzer
• Protocol analyzers (SPI, CAN, Ethernet)

• Implementation of DSP algorithms on FPGA (Radar / EW systems)

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