Design and simulate various ESD clamps (Signal & Power) and fully evaluate the high current and voltage properties of the same. Analyze the driver/receiver architecture and provide best ESD solutions for the same. Assess the fundamental ESD properties of each type of ESD circuit elements, from active diffusions to BEOL metal layers, using wafer level transmission line pulse (TLP and vf-TLP) data provided by the foundry. Provide ESD and latch-up (LUP) design rules and Guidelines for the customers. Supervise and arrange full-chip ESD design review process (Schematic and Pathfinder analysis) for each design prior to tapeout. Apply Pathfinder type ESD current density and resistance verification tool to ensure full die layout meet all ESD design rule requirements. Supervise and arrange IP/full-chip ESD design review process using PERC for each design prior to tapeout. Continually improve product design and reliability by introducing innovative ESD designs. Experience in Cadence design tools for design, layout, and verification tools. Experience in ESD analysis tools like PERC or Path-Finder or similar software tools. A BS Electrical Engineering, Microelectronics, with 2-6 years of experience, OR A MS in Electrical Engineering, Microelectronics with 3-6 years of experience, OR A Ph.D. in Electrical Engineering, Microelectronics. An MS/Ph.D. in Electrical Engineering, Microelectronics, or related field, with 2+ years of experience.
