
Design Verification Senior Staff Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
- Develop and maintain testbenches for IP, subsystem, and SoC-level verification
- Design and implement UVM-based verification environments
- Write and execute directed and random test cases
- Perform functional coverage analysis and debug failures
- Collaborate with design, architecture, and validation teams to ensure verification completeness
- Participate in code reviews, quality improvement, and problem-solving initiatives
- Strong background in IP, Subsystem and SoC verification, including methodology and testbench development
- Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++
- Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations
- Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus
- Strong analytical and problem-solving skills
- Ability to manage multiple tasks in a fast-paced environment
- Excellent communication, interpersonal, and teamwork skills
- Capable of interfacing effectively at all levels within and outside the organization
- Proactive in participating in problem-solving and quality improvement initiativesAdditional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our page.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.#LI-CP1