Job Description:90/130/150nm and higher node with PMIC layout experience.Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation.Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations.Create floorplanPerforms DRC and takes corrective actions if needed until DRC is error freePerforms LVS and takes corrective actions if needed until result is successfulPerforms layout in such a way that final result meets the foundry layout rules.Provides extracted netlist for back annotation to DE as specified in the Design document, section layout.Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout.Adds extra useful information to the Block review document, section layout.Department:Semicon (India) AssociateSkills Required:Layout Versus Schematic (LVS),Design Rule Checking (DRC),Floor Plans,Layout Designs,Cadence Virtuoso Layout Suite,Power Management Integrated Circuits (PMICs)Years Of Exp:5 to 12 YearsDesirable Skills:Layout Versus Schematic (LVS),Design Rule Checking (DRC),Floor Plans,Layout Designs,Cadence Virtuoso Layout Suite,Power Management Integrated Circuits (PMICs)Designation:Associate
