Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Bachelor's degree in electrical or computer engineering. 10+ years industry experience in ASIC IP verification using SystemVerilog and UVM. Development of verification test plans and create directed/randomized test cases. Formal verification. In implementing scoreboards, checkers, bus functional models in existing testbench environment. AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. - CEE10 Design DGS. - SDI3 Upgrade. - SDI3 Solution Design. - SDI3 Integration. - GDCE. - Coaching and Mentoring. - Innovation and Creativity. - Google GCP. - AWS Public Cloud. - Azure Public Cloud. - AWS Outpost. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world's toughest problems. You´ll be challenged, but you won't be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. learn more. Primary country and city: India (IN) || Req ID: 771287
