
Sr.Lead Silicon Design Engineer - FPGA Design
- Hyderabad, Telangana
- Permanent
- Full-time
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be implemented and verified
- Build Requirements Spec, Design spec, test plan and test spec documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to implement the new features and write the new feature tests and any required changes to the test environment
- Debug test failures to determine the root cause; work with other RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
- Minimum of 15 years of design and development experience, preferably in a customer facing role
- Minimum of 10 years of experience in FPGA VHDL and/or Verilog design, AMD technology and tools, FPGA verification and test
- Experienced in analysing customer requirements, effort estimation and committing a schedule for delivery
- Interaction with Architects, other RTL engineers and SW engineers to define system level requirements and usecases
- Leading a group of RTL engineers to deliver on customer commitments
- Experienced with Verilog, System Verilog, and C programming
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Developing UVM based verification frameworks and testbenches, processes and flows
- Experience in HW testing, including working with test equipment, logic and traffic analyzers, test generators, etc.
- Experience in designing complex systems involving one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Python, Makefile, and shell are preferred.
- Top class Bachelors or Master's degree in Electronic Engineering
- Track record of high academic achievement