Qualification: Experience Required:4 + Education: Btech/Mtech Electronics/Electrical engineering Skills/Experience: - Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR/HBM IP's -Understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies. - Goodunderstanding of CMOS and FinFETlayouts and process technology in 28nm and smaller. - Good understanding of basic ESD and latchup layout design considerations. - Familiarity with ASIC physical design flow:LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE. - Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc. - Scripting skills for layout automation is a plus - Good written and verbal communication skills in interactions with customers, and internal development teams. Responsibilities : - High SpeedDDR/HBMLayout design -- Work with DDR PHY team, package engineers and system engineers to meet design specs. - Perform scheduling duties - Work with local team to support critical layout and floorplanning requirements - Coordination duties with other layout teams both in Bangaloreto detail out layout activities and obtain layout deliverables. - Strict flow adherence and policing of internal policies to secure schedules.
