
Sr. RTL Design Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
- RTL Coding in Verilog/System-Verilog and Integrating various IP/Blocks.
- Various Quality Checks (LINT/CDC/RDC/CLP) associated with integration and IP development.
- Handling various collaterals like SDCs, UPFs, IPXACT, filelist etc.
- Provide technical support to other teams
- Relevant industry experience of around 6yrs+
- Good at Verilog/System-Verilog
- Familiarity with scripting languages like perl python, tcl or unix-shell scripting.
- Hands-on pexposure with various QC tools and comfortable in LINT/CDC/RDC closures.
- Bachelors or Masters degree in Electronics/Electrical Engineering