Principal Engineer, RTL Design
- Bangalore, Karnataka
- Permanent
- Full-time
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell.What You Can Expect
- As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the upcoming networking chips.
- Additional responsibilities will include, but not be limited to:
- Responsible for micro-architecture design and development of some of the critical IPs involved in networking chips.
- Working with Architects and Verification engineers to deliver and develop complex, high-performance and timing-critical designs through all aspects of the SoC front-end design flow (incl. timing closure and power optimization)
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
- Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience.
- Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC.
- Hands on experience in interpretive language such as Perl/Python.
- Proven track record of delivering production-quality designs on aggressive development schedules.
- Domain expertise in Ethernet packet processing, scheduler is a plus.